1. Field of the Invention.
This invention relates to compact diode logic circuits that utilize CMOS technology to perform the Boolean operations A.multidot.B and A+B.
2. Statement of the Prior Art.
The conventional CMOS logic circuits (see FIGS. 1 and 2 of the accompanying drawings and the corresponding description thereof) that perform the Boolean operations A.multidot.B and A+B are typically mechanized by a plurality (e.g. four) of CMOS field effect transistors and an inverter gate. This mechanization undesirably consumes a relatively large amount of area. Moreover, because of the relatively high inherent on-resistance of the field effect transistors, the speed of the conventional logic circuits is minimized.
No patents are known which show or disclose a CMOS logic circuit that performs the Boolean function A.multidot.B or A+B, which circuit is comprised of a field effect transistor device and a plurality of diodes that are interconnected to perform logic, like that disclosed in the subject patent application. One example of a patent which discloses CMOS diode logic gates is the following:
U.S. Pat. No. 3,986,042 Oct. 12, 1976. PA1 U.S. Pat. No. 3,621,292 Nov. 16, 1971 PA1 U.S. Pat. No. 3,638,046 Jan. 25, 1972
However, this aforementioned patent does not disclose a plurality of logic performing diodes, each receiving a respective logic level input signal to be gated according to the Boolean function A.multidot.B or A+B, as disclosed and claimed by the present invention. Other conventional circuits which include a diode connected across the conduction path of a field effect transistor device are shown in the following patents:
However, neither the circuits nor the respective diodes of the aforementioned patents are utilized to either receive input logic level signals or to perform Boolean operations, as is disclosed and claimed in the subject patent application.